1. Field of the Invention
The present invention relates to a technology for enabling high-speed transmission of signals between a plurality of LSI chips or a plurality of devices or circuit blocks within a single chip, or between a plurality of boards or a plurality of cabinets and, more particularly, to a data receiving circuit and a clock recovery circuit that uses a feedback-loop-type clock signal generating circuit.
2. Description of the Related Art
Recently, the performance of components used in computers and other information processing apparatuses has been greatly improved. In particular, dramatic improvements have been made, for example, in the performance of processors and semiconductor memory devices such as SRAMs (Static Random Access Memories) and DRAMs (Dynamic Random Access Memories). The improvements in the performance of semiconductor memory devices, processors, and the like have come to the point where system performance cannot be improved further unless the speed of signal transmission between components or elements is increased.
Specifically, the speed gap between a storage device such as a SRAM or DRAM (memory) and a processor (i.e., between LSIs), for example, has been widening year by year, and in recent years, this speed gap has been becoming a bottleneck impeding performance improvement for a computer as a whole. Furthermore, with increasing integration and increasing size of semiconductor chips, the speed of signal transmission between elements or circuit blocks within a chip is becoming a major factor limiting the performance of the chip. Moreover, the speed of signal transmission between a peripheral device and the processor/chipset is also becoming a factor limiting the overall performance of the system.
Generally, in high-speed signal transmission between circuit blocks or chips or between cabinets, a clock used to discriminate between data “0” and data “1”, is generated (recovered) at the receiving circuit. The recovered clock is adjusted by a feedback circuit in the receiving circuit so that the clock is maintained within a certain phase range with respect to the received signal in order to ensure correct signal reception at all times. The process of recovering the clock and discriminating the data using the thus recovered clock is called the CDR (Clock and Data Recovery). The CDR is the most important function for high-speed data reception, and various schemes are being studied. There is thus a strong need to provide a data receiving circuit (clock recovery circuit) capable of handling high-speed and accurate signal transmission using CDR.
To address the recent increase in the amount of data transmission between LSIs or between boards or cabinets, signal transmission speed per pin must be increased. This is also necessary to avoid an increase in package cost, etc. due to an increased pin count. As a result, inter-LSI signal transmission speeds exceeding 2.5 Gbps have been achieved in recent years, and it is now desired to achieve extremely high speeds (high-speed signal transmission) reaching or even exceeding 10 Gbps.
To speed up the signal transmission between LSIs, for example, it is required that the receiving circuit operates with adequately accurate timing for each incoming signal (for data detection and discrimination). It is known in the prior art to provide in a signal receiver circuit a clock recovery circuit (CDR) that uses a feedback loop type clock signal generating circuit in order to generate a clock (internal clock) with such accurate timing.
That is, to achieve the CDR, a feedback circuit is used that generates an internal clock for data reception, and that compares the internal clock with the phase of the data and adjusts the phase of the internal clock based on the result of the phase comparison.
The prior art and the related art and their associated problems will be described in detail later with reference to the accompanying drawings.